VLSI Implementation of Pipelined PE Systolic Array-Based 3x3 Matrix Multiplication for Deep Neural Network Accelerator
Year: 2025
Type: conference-paper
Authors: Elango S, Stephen Sagayaraj A, Surendhar D, Nivethitha M
Institution: Bannari Amman Institute of Technology
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4410986582