Delay and Power Optimization in 8-Bit ALU Using Reversible Logic
Year: 2025
Type: conference-paper
Authors: Uppari Sathwik, Somishetty Bhanu Teja, Bhalke Pooja, Kiran Mannem, Manchalla.O.V.P.kumar, S.Ravi Chand
Language: English
Subfield: Computational Theory and Mathematics
Field: Computer Science
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4410987474