Work

A 64.7 nA, –65dB@1 kHz, and Dual-Output CMOS Voltage Reference With Multi-Loop Active Load Without Trimming

Year: 2025

Type: article

Source: IEEE Transactions on Circuits & Systems II Express Briefs

DOI: 10.1109/tcsii.2025.3577401

Authors: Yanhan Zeng, Cailin Yu, Jingci Yang, Yanshen Luo, Bincheng Lei, Yongfu Li

Institutions: Guangzhou University, Shanghai Jiao Tong University

Language: English

Topic: Analog and Mixed-Signal Circuit Design

Subfield: Biomedical Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funders: Natural Science Foundation of Guangdong Province, Science and Technology Planning Project of Guangdong Province, National Natural Science Foundation of China-Guangdong Joint Fund

Awards: G1891272988, G7513031245, G7862264362

OpenAlex ID: W4411086255

FWCI: 0.964

Cites: 18

Cited by: 4

Related to: 10