Year: 2025
Type: conference-paper
Abstract: Current memory tiering systems mitigate asymmetric latency through page migration between tiers. While this approach effectively hides latency, it overlooks scenarios where latency could potentially be tolerated. We propose that an efficient system should integrate both latency reduction (migration) and latency tolerance strategies. Our research demonstrates the effectiveness of prefetchers in tolerating latency within such systems, highlighting their importance in the design of high-performance memory tiering solutions.
Authors: Musa Unal, Vishal Gupta, Yueyang Pan, Yujie Ren, Sanidhya Kashyap
Institution: École Polytechnique Fédérale de Lausanne
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W4411091774