Year: 2025
Type: article
Abstract: This project presents the design and synthesis of a fault-tolerant neuromorphic system using memristor-based technology. The primary objective is to develop a low-power, highly efficient hardware model that mimics biological neural behavior while maintaining robustness against faults. By integrating a TCM (Trellis Coded Modulation) encoder with a memristor-based processing unit, the system achieves improved error correction and reliability. The proposed design was implemented using Verilog HDL and synthesized through industry-standard EDA tools, providing insights into power consumption, area utilization, and timing performance. The synthesis reports demonstrate that the system operates within acceptable power limits while occupying minimal silicon area, making it ideal for resource-constrained environments. The timing analysis confirms that the design meets setup and hold requirements, ensuring stable and reliable operation. This work contributes to the growing field of neuromorphic engineering and provides a strong foundation for future developments in energy-efficient and fault-resilient AI hardware systems.
Author: Anusha Sowpati
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W4411114147