A Power and Area Efficient Analog Classifier for Electrical Impedance Tomography Applications
Year: 2025
Type: article
Abstract: This paper introduces a methodology tailored to analog hardware architecture for implementing an artificial neural network. The core components of the architecture include voltage-mode circuit for the input layer and current-mode circuits for the hidden layers and the decision making. Specifically, the main part of the architecture comprise a Gaussian function circuit, a Sigmoid function circuit, an analog multiplier, and current mirrors. A current comparator is employed as the decision-making circuit. The operational principles of the architecture are detailed and realized in an energy-efficient configuration, operating at just 865 nW with low supply rails of 0.6V. The proposed design has been tested on real-world electrical impedance tomography classification tasks, achieving a classification accuracy exceeding $$94.22\%$$ . The architecture is implemented using 90nm CMOS technology and developed with the Cadence IC Suite for schematic and layout design. Monte Carlo simulations, incorporating process variations and mismatches, along with corner-case analysis, are conducted to verify the robustness of the classifier. A comparative analysis of post-layout simulation results with an equivalent software-based classifier and existing literature validates the accuracy and reliable operation of the proposed architecture.
Language: English
Subfield: Biomedical Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
Estimated APC paid: $3,190
Funders: European Commission, NextGenerationEU
Award: G6276162139
OpenAlex ID: W4411147956