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Overcoming Charge Sharing, Race Condition, and Noise Sensitivity in Ternary DDCVSL Circuits

Year: 2025

Type: article

Abstract: Dynamic Differential Cascode Voltage Switch Logic (DDCVSL) is a circuit design that combines static DCVSL with dynamic logic to achieve the benefits of both simultaneously. It provides a robust structure and can be used in high-performance circuits due to its small size and high speed. However, dynamic logic has lower noise tolerance than its static counterpart and faces issues such as charge sharing and race conditions. These challenges are even more problematic in ternary logic, where voltage levels are closer to each other. This paper applies some well-known, promising binary techniques tackling these problems to ternary DDCVSL. The effectiveness of these techniques in ternary logic is put under careful examination. Simulation results show that the application of noise enhancement techniques increases the tolerance of the DDCVSL circuit by 1.5X and 4X, respectively, and also prevents race and charge sharing.

Source: Journal of Integrated Circuits and Systems

DOI: 10.29292/jics.v20i1.917

Authors: Nooshin Azimi, Reza Faghih Mirzaee, Keivan Navi, Amir Masoud Rahmani

Institutions: Islamic Azad University, Tehran, Islamic Azad University, Science and Research Branch, Islamic Azad University, Shahr-e-Qods Branch, Shahid Beheshti University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: diamond

OpenAlex ID: W4411169597

FWCI: 0.225

Cites:

Cited by: 1

Related to: 10