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Design And Analysis Of High-Performance 16-Bit Hybrid Adder Using Ksa & Hca Adder With Domino Logic

Year: 2025

Type: conference-paper

Source: International Conference on Advancements in Electrical, Electronics, Communication, Computing and Automation (ICAECA)

DOI: 10.1109/icaeca63854.2025.11012362

Authors: N. Prakash, A. Sathya, S. Swathi Sree, C. Pradeep, S. Boopathy, R. Krishnaveni

Institution: Kumaraguru College of Technology

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4411204241

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