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Design of Low Power and High Speed 1-Bit Full Subtractor Using Zipper Logic Technology

Year: 2025

Type: conference-paper

Source: International Conference on Smart Systems for Applications in Electrical Sciences (ICSSES)

DOI: 10.1109/icsses64899.2025.11009372

Authors: Buchepalli Sai Teja, Madhusudan Singh

Institution: National Institute of Technology Nagaland

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4411205933

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