Novel Technique to Minimize Edge Delay and Leakage Power in CMOS Adder Circuits Using 22nm Technology
Year: 2025
Type: conference-paper
Authors: Prasenjit Deb, Bapi Debnath, Aryalekshmi B N
Institutions: REVA University, HKBK College of Engineering
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4411208096