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Efficient Design and Functional Testing of a 32-Bit RISC Processor in Verilog

Year: 2025

Type: conference-paper

Source: International Conference on Smart Systems for Applications in Electrical Sciences (ICSSES)

DOI: 10.1109/icsses64899.2025.11009267

Authors: Saravanakumar C, Mohanakrishnan E, Manoj Kumar D, Jayasri K, Jobitha Lakshmi J

Institution: SRM Institute of Science and Technology

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4411208158

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