A novel 7-level SCMLI with selective harmonic elimination via war strategy optimization
Year: 2025
Type: article
Abstract: This paper introduces a seven-level switched capacitor multilevel inverter that achieves triple voltage gain while reducing the number of components, employing a single DC source, two switched capacitors, and ten semiconductor switches. The War Strategy Optimization (WSO) algorithm is employed for selective harmonic elimination (SHE), enhancing switching angles with swift convergence and reducing total harmonic distortion (THD) to around 11%. The inverter features built-in self-voltage balancing with zero voltage and zero current switchings (ZVS/ZCS), eliminating additional balancing circuits and minimizing inrush currents. The test results for 48 V input generates a maximum output voltage of 144V at 50Hz, under dynamic load and modulation conditions, validating the robustness of the design. Analysis indicates that the suggested SCMLI features a reduced peak inverse voltage (PIV) and necessitates fewer components, rendering it a more cost-effective option for high-power and renewable energy applications.
Source: Results in Engineering
Authors: Ankit Singh, Vibhu Jately, Peeyush Kala, Jyoti Joshi, Nitin Kumar Saxena, Shashank Mishra, Pavan Khetrapal, Brian Azzopardi
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $1,940
OpenAlex ID: W4411263115