Work

Graphitron: A Domain Specific Language for FPGA-Based Graph Processing Accelerator Generation

Year: 2025

Type: conference-paper

Abstract: Due to hardware customization capabilities, FPGA-based graph processing accelerators achieve significantly higher energy efficiency than many general-purpose computing engines. However, designing these accelerators remains a substantial challenge for high-level users. To overcome the programming barrier, FPGA-based accelerator design frameworks on top of generic graph processing programming models have been developed to automate accelerator generation through pre-built templates. However, they often tightly couple graph processing algorithms, programming models and processing paradigms, and accelerator architectures, which severely limits the expression scope of the algorithms and may also restrict the performance when the generated accelerators fail to suit dynamic processing patterns of the graph processing algorithms.

Source: ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

DOI: 10.1145/3735452.3735533

Authors: Xinmiao Zhang, Zheng Feng, Shengwen Liang, Xinyu Chen, Lei Zhang, Cheng Liu

Institutions: Chinese Academy of Sciences, Institute of Computing Technology, University of Chinese Academy of Sciences, The Hong Kong University of Science and Technology (Guangzhou)

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: hybrid

Funders: National Natural Science Foundation of China, Chinese Academy of Sciences, National Key Research and Development Program of China