Work

A 5.8-GHz 4.8-mW −247.1dB-FoM DTC-Free Sampling ΔΣ Fractional-N PLL With Embedded Phase Interpolation

Year: 2025

Type: article

Source: IEEE Transactions on Circuits & Systems II Express Briefs

DOI: 10.1109/tcsii.2025.3581020

Authors: Ye Wang, Jingcheng Tao, Chun-Huat Heng

Institution: National University of Singapore

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funders: NXP Semiconductors, Agency for Science, Technology and Research

OpenAlex ID: W4411405148

FWCI:

Cites: 17

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Related to: 10