Work

Design of 8 bit Arithmetic Logic Unit for Signal Processing Applications using Verilog

Year: 2025

Type: conference-paper

Source: International Conference on Pervasive Computing and Social Networking (ICPCSN)

DOI: 10.1109/icpcsn65854.2025.11035908

Authors: Ujwala Ghodeswar, Ashwini Gajbhiye

Institution: Yeshwantrao Chavan College of Engineering

Language: English

Topic: Embedded Systems and FPGA Applications

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4411447045

FWCI:

Cites: 7

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Related to: 10