Work

Design and Implementation of a Low-Power 4-Bit Synchronous Up Counter Using Gate-Diffusion Input Technology

Year: 2025

Type: conference-paper

DOI: 10.1109/icfts62006.2025.11031998

Authors: Senthil Murugan M, Tharasi Sandhya, T. Siva, Venika R J

Institution: St. Joseph's Institute of Technology

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4411484513

FWCI:

Cites: 6

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Related to: 10