Optimized Design of Clock-Gated D Flip-Flop using Transmission Gate
Year: 2025
Type: conference-paper
Authors: Jeevitha R, Mohankumar M, Gayathri Devi B, Mohammed Adhil H
Institution: Sri Eshwar College of Engineering
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4411599999