Work

An Expandable Digital Delay Line using Phase Interpolator with Duty Cycle Correction Capability

Year: 2025

Type: conference-paper

Source: IEEE International Symposium on Circuits and Systems proceedings

DOI: 10.1109/iscas56072.2025.11043284

Authors: Shinya Nagasaki, Ryo Kishida, Takefumi Yoshikawa

Institution: Toyama Prefectural University

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4411724855

FWCI: 2.358

Cites: 23

Cited by: 1

Related to: 10