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A High Performance Dual-Wordline RRAM Macro with Replica Bitline Delay Control Circuit

Year: 2025

Type: conference-paper

Source: IEEE International Symposium on Circuits and Systems proceedings

DOI: 10.1109/iscas56072.2025.11044233

Authors: Honghu Yang, Yongkang Han, Tianci Cai, Chengshuo Yu, Keji Zhou, Jianguo Yang

Institutions: Shanghai Zhangjiang Laboratory, Zhangjiang Laboratory

Language: English

Topic: Advanced Memory and Neural Computing

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funders: National Natural Science Foundation of China, Research and Development

OpenAlex ID: W4411724858

FWCI: 4.717

Cites: 15

Cited by: 2

Related to: 10