Work

A 4kb 4T eDRAM with Balanced Retention Time Adjustment

Year: 2025

Type: conference-paper

Source: IEEE International Symposium on Circuits and Systems proceedings

DOI: 10.1109/iscas56072.2025.11043825

Authors: Sayan Kumar, Dennis Andrade-Miceli, Chawin Khongprasongsiri, Teerachot Siriburanon, R. Bogdan Staszewski

Institution: University College Dublin

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funder: Science Foundation Ireland

OpenAlex ID: W4411724932

FWCI: 2.358

Cites: 1

Cited by: 1

Related to: 10