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A Low-Power Sparse Deep Learning Accelerator with Optimized Data Reuse

Year: 2025

Type: conference-paper

Source: IEEE International Symposium on Circuits and Systems proceedings

DOI: 10.1109/iscas56072.2025.11043222

Authors: Kai-Chieh Hsu, Tian-Sheuan Chang

Institution: National Yang Ming Chiao Tung University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4411725037

FWCI:

Cites: 12

Cited by:

Related to: 10