VeriBench: Benchmarking Large Language Models for Verilog Code Generation and Design Synthesis
Year: 2025
Type: conference-paper
Authors: Mihir Agarwal, Zaqi Momin, Kailash Prasad, Joycee Mekie
Institution: Indian Institute of Technology Gandhinagar
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4411725046