Work

Nanomechanical Relay-based Switchblock For FPGA Interconnect

Year: 2025

Type: conference-paper

Abstract: Reprogrammable non-volatile nanomechanical (NEM) switches have single pole double throw functionality alongside zero standby power that allows the creation of four-way switch nodes made of four NEM switches as opposed to 36 or higher for a SRAM-based implementation. The reduced device count per switch node and accompanying reductions in dynamic power, in turn, allows the creation of island-style FPGA switchblocks with more flexibility than traditional switchblocks by enabling switch matrices fully populated with switch nodes. Simulations for a matrix switchblock within a Stratix IV architecture showed an average reduction of over 40% in the channel width and total critical path wire length, as well as a reduction of nearly 50% in total wire length, over a Wilton topology switchblock. The improved routing efficiency results in more efficient mapping, reduced critical path latency, and an overall reduction in the chip size to map a given function. These improvements, in combination with near total elimination of leakage power, makes a compelling case for NEM-CMOS FPGAs, especially for edge computing applications where energy and footprint constraints are far more stringent.

Source: IEEE International Symposium on Circuits and Systems proceedings

DOI: 10.1109/iscas56072.2025.11043259

Authors: Victor Marot, Dinesh Pamunuwa

Institution: University of Bristol

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: green