Work

A 40 Gb/s Adaptive CTLE Using a Sub-Sampled PAM-4 Clock Recovery Circuit in 65nm CMOS

Year: 2025

Type: conference-paper

Source: IEEE International Symposium on Circuits and Systems proceedings

DOI: 10.1109/iscas56072.2025.11044025

Authors: Alok Kumar, Ishan Mishra, Tejavanth Kothani, Rajshekhar Mukherjee, Midhun V, Shalabh Gupta

Institution: Indian Institute of Technology Bombay

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4411725491

FWCI: 4.717

Cites: 12

Cited by: 2

Related to: 10