Work

A Reference Double-Sampling PLL-Based Eight Phase Clock Generator Achieving 0.18mW/GHz/phase and -251.9dB FOMJitter-N

Year: 2025

Type: conference-paper

Source: IEEE International Symposium on Circuits and Systems proceedings

DOI: 10.1109/iscas56072.2025.11043253

Authors: Sirou Li, Weijia Zeng, Kaiyun Cao, Liangjian Lyu, C.-J.Richard Shi

Institutions: Fudan University, East China Normal University

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funders: Chinese Academy of Sciences, Science and Technology Commission of Shanghai Municipality

OpenAlex ID: W4411725718

FWCI: 4.717

Cites: 14

Cited by: 2

Related to: 10