Work

A 62.8 TOPS/W FP-INT Digital Computing-in Memory Processor with Bit-Reordered Adder Tree and Low Active Hierarchical Accumulator

Year: 2025

Type: conference-paper

Source: IEEE International Symposium on Circuits and Systems proceedings

DOI: 10.1109/iscas56072.2025.11043177

Authors: Sunjoo Whang, Sangwoo Ha, Soyeon Um, Sangjin Kim, Hoi-Jun Yoo

Institution: Korea Advanced Institute of Science and Technology

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4411725928

FWCI: 2.358

Cites: 11

Cited by: 1

Related to: 10