Work

Design and Performance Analysis of 14T Low Power and Less Area 1-bit Hybrid Full Adder

Year: 2025

Type: conference-paper

Source: International Conference on Recent Advances in Electrical, Electronics, Ubiquitous Communication, and Computational Intelligence (RAEEUCCI)

DOI: 10.1109/raeeucci63961.2025.11048320

Authors: R Senthamizh Selvi, N Charu Priya, R Harini, S S Sachin Dev

Institutions: Easwari Engineering College, PSG INSTITUTE OF TECHNOLOGY AND APPLIED RESEARCH

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4411726299

FWCI: 2.3

Cites: 15

Cited by: 1

Related to: 10