Work

Arithmetic Logic Unit using 4-bit Vedic Multipliers with Multiplexers

Year: 2025

Type: conference-paper

Source: International Conference on Recent Advances in Electrical, Electronics, Ubiquitous Communication, and Computational Intelligence (RAEEUCCI)

DOI: 10.1109/raeeucci63961.2025.11048334

Authors: Viraj Deshpande, Raghav Rajput, Arijit Bardhan Roy

Institution: SRM Institute of Science and Technology

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4411726343

FWCI: 2.358

Cites: 7

Cited by: 1

Related to: 10