Work

A PVT-Insensitive 7-Bit Coarse-Fine Ratio-Metric Digital-to-Time Converter for Fractional-N Phase-Locked Loops in 65-nm CMOS

Year: 2025

Type: conference-paper

Source: IEEE International Symposium on Circuits and Systems proceedings

DOI: 10.1109/iscas56072.2025.11043926

Authors: Shenjian Zhang, Chenming Zhang, Hao Luo, Shengtao Yi, Xuewei Ding, Zhirui Zong

Institution: The Hong Kong University of Science and Technology (Guangzhou)

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funder: National Natural Science Foundation of China

OpenAlex ID: W4411726837

FWCI:

Cites: 16

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Related to: 10