Work

CIT-CTPlacer: An Analytical RDL Chiplet-Terminal Co-Placement Algorithm for Large-Scale 2.5D IC

Year: 2025

Type: conference-paper

Source: IEEE International Symposium on Circuits and Systems proceedings

DOI: 10.1109/iscas56072.2025.11044301

Authors: Xihao Liang, Yujie Wang, Xupengkai Lu, Lang Feng, Jixiang Zhu, Ying Wang, Yinhe Han

Institutions: Chinese Academy of Sciences, Institute of Computing Technology, Sun Yat-sen University

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funder: National Natural Science Foundation of China

OpenAlex ID: W4411727193

FWCI:

Cites: 12

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Related to: 10