Work

A 4.5-Track Standard Cell Library with Buried Power Rails in 7nm Node

Year: 2025

Type: conference-paper

Source: IEEE International Symposium on Circuits and Systems proceedings

DOI: 10.1109/iscas56072.2025.11043668

Authors: Kai-Jie Tong, Ting-An Jian, Shang-Mou Zhou, Yi-Jia Wu, Bo-Xiang Yang, Meng-Ru Lin, Ming-Yi Huang, Shi-Xian Tang, Ya-Zhu Yang, Zheng-Jie Peng, Yu-Cheng Lin, Rung-Bin Lin

Institution: Yuan Ze University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4411727411

FWCI:

Cites: 18

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Related to: 10