Work

Design of Power and Area Optimized 16 – bit Multiplier

Year: 2025

Type: conference-paper

Source: International Conference on Innovative Trends in Information Technology (ICITIIT)

DOI: 10.1109/icitiit64777.2025.11040485

Authors: Tushar R, Shruti Sivaramakrishnan, Ramesh S R

Institution: Amrita Vishwa Vidyapeetham

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4411727939

FWCI: 7.075

Cites: 17

Cited by: 3

Related to: 10