Year: 2025
Type: conference-paper
Abstract: In this work, we carried out an overlay-aware variation study on Flip FET (FFET) considering the impact on RC parasitics induced by the lithography misalignment in backside processes, and benchmarked it with CFET in terms of the power-performance (PP) and variation sources. The iso-leakage frequency degrades up to 2.20% with layout misalignment of 4 nm. It's found that the Drain Merge resistance degrades significantly with misalignment increasing and is identified as the major variation source. Through careful DTCO with design rule optimization, the variation can be greatly suppressed, while the resistance fluctuation of the DM also drops substantially. Monte Carlo random experiments were also conducted, validating the variation reduction. Comparing with the CFET featuring selfaligned gate and much less overlay induced misalignment, fortunately, FFET's PP is still better except when misalignment reaches 8 nm, which is out of spec and nearly impossible. Considering the variabilities induced by the high aspect ratio processes, CFET still faces big challenges compared with FFET.
Authors: Wanyue Peng, Haoran Lu, Jingru Jiang, Jiacheng Sun, Ming Li, Runsheng Wang, Heng Wu, Ru Huang
Institution: Peking University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
Awards: G7568304601, G8344861315
OpenAlex ID: W4411799105