Evaluation of Logic Locking Schemes Against Oracle-Less Machine Learning Attacks at the RTL Level
Year: 2024
Type: article
Abstract: Logic locking is frequently used to protect integrated circuits against reverse engineering and intellectual property theft. However, classic gate-level locking approaches are becoming more vulnerable to machine learning (ML)-based attacks that exploit design patterns to recover hidden keys. To reduce these concerns, RTL-level locking solutions such as ASSURE have been proposed that attempt to conceal logic earlier in the design cycle. Despite their potential, these strategies are mostly unexplored in terms of real resistance to ML-driven attacks. In this study, we conducted an empirical investigation of the ASSURE RTL locking mechanism, with a focus on its effectiveness against ML-based key recovery attempts. We tested locked versions of benchmark circuits by extracting design attributes and training supervised algorithms to predict hidden keys in realistic threat scenarios. Our findings show that RTL locking provides greater robustness than gate-level locking, with lower prediction accuracy from ML classifiers and tolerable design overhead. This early study supports the use of RTL-level obfuscation to improve hardware security and encourages further research into its implementation and optimization.
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W4412036283