Work

Area and Power Efficient, Scalable Offset Compensation Scheme for High-Speed, High Resolution Time Interleaved ADC

Year: 2025

Type: conference-paper

Source: IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)

DOI: 10.1109/vlsisata65374.2025.11070033

Authors: Gunjan Mandal, Katepalli Naveen Kumar, Nukamreddy Venkata Subba Reddy

Institution: Intel (India)

Language: English

Topic: Analog and Mixed-Signal Circuit Design

Subfield: Biomedical Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4412404691

FWCI: 2.903

Cites: 9

Cited by: 1

Related to: 10