Work

Ternary CMOS Compact Model for Low Power On-Chip Memory Applications

Year: 2025

Type: article

Abstract: In this work, we present a tunneling based ternary CMOS (T-CMOS) compact model for low power ternary-SRAM (T-SRAM) design using CMOS technology. By designing compact model parameters of band-to-band tunneling current (IBTBT) according to effective doping concentration of T-CMOS, more accurate current model has been obtained in comparison with the conventional IBTBT models. In addition, parasitic capacitance models are obtained for transient operation. Comparing model and experimental data, it enables the prediction of T-CMOS performance under various VDD conditions. The model is validated to be more suitable for T-CMOS with low power on-chip memory applications.

Source: IEEE Journal of the Electron Devices Society

DOI: 10.1109/jeds.2025.3588398

Authors: Young-Eun Choi, Woo-Seok Kim, Myoung Kim, Junyoung Park, Min Woo Ryu, Kyung Rok Kim

Institution: Ulsan National Institute of Science and Technology

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: gold

Estimated APC paid: $1,350

Funders: Ulsan National Institute of Science and Technology, National Research Foundation of Korea