Work

Reconciling Hardware Transactional Memory and Persistent Programming with Buffered Durability

Year: 2025

Type: conference-paper

Abstract: Hardware Transactional Memory (HTM) simplifies concurrent programming and can accelerate multithreaded execution through lock elision. Non-Volatile Memory (NVM) combines the speed and byte addressability of DRAM with the durability of storage, enabling the construction of high-performance, persistent data structures. Unfortunately, the write-back instructions typically needed to ensure post-crash consistency in NVM cause HTM transactions to abort, precluding the straightforward combination of HTM and persistent data structures. The problem goes away on machines with persistent caches, but these require special battery-backed circuitry and are far from commonplace.

Source: ACM Symposium on Parallelism in Algorithms and Architectures (SPAA)

DOI: 10.1145/3694906.3743321

Authors: Mingzhe Du, Ziheng Su, Michael L. Scott

Institution: University of Rochester

Language: English

Topic: Distributed systems and fault tolerance

Subfield: Computer Networks and Communications

Field: Computer Science

Domain: Physical Sciences

Open Access status: hybrid

Funders: National Science Foundation, Universitas Brawijaya

Awards: CNS Core: Medium: Reimagining the Storage Stack for Emerging Memory Technologies, CNS Core: Medium: Operating System Modularity for Safety and Performance on Existing Commodity Hardware, G5713153527