Work

Optimizing True Random Number Generation on Fpgas: Leveraging Dynamic Clock Phase Shifts and Fast Carry Chains for Enhanced Performance and Efficiency in 32-Bit and 64-Bit Implementations

Year: 2025

Type: conference-paper

Source: International Conference in Advances in Power, Signal, and Information Technology (APSIT)

DOI: 10.1109/apsit63993.2025.11086139

Authors: Ankur Beohar, Trapti Sharma, Pallabi Sarkar, Rishabh Kumar Gupta, Deepak Kumar Das, Himanshu Ranjan

Institution: VIT Bhopal University

Language: English

Topic: Physical Unclonable Functions (PUFs) and Hardware Security

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4412624038

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