Work

A 40GS/s 8bit Time-Interleaved Time-Domain ADC Featuring SFDR-Enhanced Sample-and-Hold Circuit and Power-Efficient Adaptive Pulse Generator in 28nm CMOS

Year: 2025

Type: conference-paper

Source: Digest of papers - IEEE Radio Frequency Integrated Circuits Symposium

DOI: 10.1109/rfic61188.2025.11082794

Authors: Chenghao Zhang, Maliang Liu, Yuan Chang, Yihang Yang, Yintang Yang, Yong Chen

Institutions: Xidian University, Tsinghua University

Language: English

Topic: Analog and Mixed-Signal Circuit Design

Subfield: Biomedical Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4412624766

FWCI: 2.903

Cites: 8

Cited by: 1

Related to: 10