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Energy-Efficient GNRFET-Based Ternary Full Adder for Next-Generation Integrated Circuits

Year: 2025
Type: article
Abstract: GNRFETs demonstrate two key advantages for nextgeneration VLSI circuits through improved carrier mobility and decreased power requirements.The integration of GNRFETs into VLSI design processes faces three significant physical design challenges because of fabrication incompatibility and heat management requirements.GNRFET integration requires successful resolution of these issues to achieve their deployment in modern VLSI technologies.Ternary operations consume much lesser power, fewer transitions and switching activities than the binary logic system.[1][2][3][4][5] Ternary logic uses three different logic levels to function.In ternary circuits, the ground GND level is low, while the supply voltage VDD is at a high level.Midway point voltage is at half the supply voltage VDD/2.This middle point is labeled as "0.5" to represent the middle value.This third voltage level, the middle point VDD/2, minimizes the number of gates which makes connections in the circuit less complicated.The remaining section of this paper is stated as follows: section II illustrates the literature survey, section III highlights the GNRFET based Ternary Logic concepts,
Language: English
Open Access status: diamond
OpenAlex ID: W4412763874
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