Work

Below 10A CMOS- Double CFETs (ↄc-FETs) with Dielectric-Wall-Stress by Isolation-Last Process for 0.0069 um2 of SRAM-Cell Design

Year: 2025

Type: conference-paper

Source: Silicon Nanoelectronics Workshop (SNW)

DOI: 10.23919/snw65111.2025.11097233

Authors: Yi-Sung Chen, Yu-Shang Shih, Hao-Ming Huang, Ting-Kuan Ma, E Ray Hsieh

Institutions: National Central University, National Yang Ming Chiao Tung University

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4412803398

FWCI:

Cites: 1

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Related to: 10