Work

Optimizing CFET Parasitic Capacitance and Performance Through Middle Dielectric Isolation and Middle via Integration

Year: 2025

Type: conference-paper

Source: Silicon Nanoelectronics Workshop (SNW)

DOI: 10.23919/snw65111.2025.11097213

Authors: Meng-Lin Wu, Yu-Cheng Lu, Vita Pi-Ho Hu

Institution: National Taiwan University

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4412803526

FWCI:

Cites: 1

Cited by:

Related to: 10