A Compact Model for Program Operation of Gate-All-Around Barrier-Engineered Charge-Trapping NAND Flash Memory in the FN-Tunneling Regime
Year: 2025
Type: article
Abstract: We introduce a compact model for characterizing the transient program operation of Gate-All-Around (GAA) Barrier-Engineered charge-trapping NAND flash (BE-CTNF) memory, especially in the FN-tunneling regime. Differing from prior models, our approach involves the calculation of threshold voltage shift attributed to each trapping layer, taking into account GAA structure of the cell and, at the same time, electron trapping within the oxide-nitride-oxide (ONO) tunneling layer. We validated our model through a comprehensive analysis of various physical parameters, with calibration to the results from the 3-D TCAD simulation.
Authors: Haechan Choi, Hyungcheol Shin
Institution: Seoul National University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $1,350
OpenAlex ID: W4412939732