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A 6+ Ghz 128 Kb Multi-Port L1 Cache Using Ground Rule Clean 10T Bitcells in 5Nm Technology

Year: 2025

Type: conference-paper

DOI: 10.23919/vlsitechnologyandcir65189.2025.11074981

Authors: Rajiv Joshi, John Davis, Gregory Fredeman, Brian Yavoich, Uma Srinivasan, Russell Hayes, Antonio Pelella, Zhiying Chen, Paul Bunce, Dongho Lee, Ismael Cervantes, Genadi Tverskoy, Derek Leu, Juergen Pille, Bill Huott, Steve Kim

Institutions: IBM (United States), IBM Research - Thomas J. Watson Research Center, IBM (Germany)

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4412963105

FWCI: 2.358

Cites:

Cited by: 1

Related to: 10