Work

A 3nm FinFET 563kbit 35.5Mbit/mm2 Dual-Rail SRAM with 3.89pJ/Access High Energy Efficient andμW/Mbit 1-Cycle Latency Low-Leakage Mode

Year: 2025

Type: conference-paper

DOI: 10.23919/vlsitechnologyandcir65189.2025.11074969

Authors: Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Kazuto Mizutani, Masaya Hamada, Yuichiro Ishii, Koji Nii, Mark Zhou, J.C. Liu, Chien-Yu Huang, Kang-Hui Peng, Yu-Hao Hsu, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Institution: Taiwan Semiconductor Manufacturing Company (Taiwan)

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4412963232

FWCI: 4.717

Cites:

Cited by: 2

Related to: 10