3D Stacked FET (3DSFET) Logic and SRAM Technology Featuring Single Diffusion Break (SDB) and Back Side Interconnect (BSI) at 48 nm CPP for Advanced Mobile and High Performance Computing (HPC) Applications
Year: 2025
Type: conference-paper
Authors: Daewon Ha, J. Park, J. Park, S. Han, D. Yeon, M. Kim, S. Park, J. Yun, K. Hwang, J. Park, J. Yang, S. Lee, J.W. Jeong, C. Yun, J. Bae, D. Huh, H. Choi, S. Baik, S. Ji, H. Park, J. Seo, J. Koo, Y. Choi, H. Yoon, A. Kim, S. Son, S. Han, S. Lee, G. Kim, S. Han, S.H. Lee, S.W. Park, S. Hyun, S.J. Ahn, J.H. Song
Institutions: Samsung (South Korea), Samsung Electronics (South Korea)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4412963719