Year: 2025
Type: conference-paper
Abstract: We present a 7-bit wireline source-series terminated (SST) digital-to-analog converter (DAC) in 5nm FinFET CMOS. The number of unit cells is reduced by employing SST cells with relative weight 1 and 4. From an eight-phase clock, each unit cell creates clock pulses which are in turn used to control the three-stage 8: 1 multiplexer. At 150 GSa/s, the ENOB was measured to be 4.1bit for a 72.8GHz sinewave. The DAC consumes 621mW from a 0.9V and 0.96V supply. Eye diagrams of 150Gbit/s non-return to zero modulation and 300Gb/s P AM-4 are measured, pre-equalized using a 10-tap feedforward equalizer.
Institutions: Ghent University, IMEC
Language: English
Subfield: Biomedical Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W4412964570