A Fractional-N Digital-PLL Based on a Power-Gated Ring-Oscillator and a Frequency-Stabilizing Loop Achieving 74fs Jitter Under $3 \text{mV}_{\text{pp}}$ Supply Ripple
Year: 2025
Type: conference-paper
Authors: M. Rossoni, R. Moleri, D. Lodi Rizzini, P. Salvi, S. Gallucci, G. Castoro, F. Tesolin, A. L. Lacaita, S. M. Dartizio, S. Levantino
Institution: Politecnico di Milano
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4412964609