A 0.5-0.8V 10-85 MS/s 12-Bit SAR ADC in 22nm FDSOI Utilizing an Inverter-Based Comparator Architecture
Year: 2025
Type: conference-paper
Abstract: A low-noise high-speed inverter-based comparator architecture integrated within a SAR ADC is proposed, enabling the ADC to operate down to 0.5 V supply at a state-of-the-art Nyquist rate of$10 \text{MS} / \mathrm{s}$, while still achieving 9.5 ENOB and a Walden FoM of$2.0 \text{fJ} /$conv - step. At its typical supply of 0.8 V, the ADC demonstrates 9.9 ENOB at a Nyquist rate of$85 \text{MS} / \mathrm{s}$, with a Walden FoM of$3.6 \text{fJ} /$conv-step.
Institution: University of Twente
Language: English
Subfield: Biomedical Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W4412964923