Work

Enhancing Power-Performance-Area Scaling of Std-Cell, SRAM, and Analog Designs Through Design-Technology Co-Optimization

Year: 2025

Type: conference-paper

DOI: 10.23919/vlsitechnologyandcir65189.2025.11074818

Authors: Jie Deng, Deepak Sharma, Jun Yuan, Hao Wang, Xiao-Yong Wang, Bruce Lim, Chulmin Jung, Jason Cheng, Yandong Gao, Hadi Rasouli, Anatoly Kauffman, Yuming Chiang, Raghava Denduluri, Giri Nallapati, PR. Chidi Chidambaram

Institution: Qualcomm (United States)

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4412965751

FWCI: 6.901

Cites:

Cited by: 3

Related to: 10